Memory transistor with multiple charge storing layers and a high work function gate electrode
US8063434B1 · kind B1 · utility
75Cited by
6References
9Claims
0Family size
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Key dates
| Filing date | May 13, 2008 |
| Grant date | Nov 22, 2011 |
| Priority date | — |
| Expiry date | Sep 16, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/349
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An embodiment of a semiconductor device includes a non-volatile memory transistor including an oxide-nitride-oxide (ONO) dielectric stack on a surface of a semiconductor substrate, the ONO dielectric stack comprising a multilayer charge storage layer including a silicon-rich, oxygen-lean top silicon oxynitride layer and a silicon-rich, oxygen-rich bottom silicon oxynitride layer, and a metal oxide semiconductor (MOS) logic transistor including a gate oxide and a high work function gate electrode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.