Assembly of nanoscaled field effect transistors
US8063450B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 19, 2007 |
| Grant date | Nov 22, 2011 |
| Priority date | — |
| Expiry date | Sep 19, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/85
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
The present invention relates to vertical nanowire transistors with a wrap-gated geometry. The threshold voltage of the vertical nanowire transistors is controlled by the diameter of the nanowire, the doping of the nanowire, the introduction of segments of heterostructures in the nanowire, the doping in shell-structures surrounding the nanowire, tailoring the work function of the gate stack, by strain engineering, by control of the dielectrica or the choice of nanowire material. Transistors with varying threshold voltages are provided on the same substrate, which enables the design of advanced circuits utilizing the shifts in the threshold voltages, similar to the directly coupled field logic.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.