Identifying and accessing individual memory devices in a memory channel
US8064237B2 · kind B2 · utility
6Cited by
14References
26Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 21, 2010 |
| Grant date | Nov 22, 2011 |
| Priority date | — |
| Expiry date | Dec 21, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0646
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment of the invention, a memory integrated circuit is provided including a memory array, a register, and control logic coupled to the register. The memory array in the memory integrated circuit stores data. The register includes one or more bit storage circuits to store one or more identity bits of an identity value. The control logic provides independent sub-channel memory access into the memory integrated circuit in response to the one or more identity bits stored in the register.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.