Nonvolatile NAND-type memory devices including charge storage layers connected to insulating layers
US8064259B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 13, 2009 |
| Grant date | Nov 22, 2011 |
| Priority date | — |
| Expiry date | Feb 9, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0466
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A nonvolatile memory device includes a word line group including a plurality of middle word lines and an edge word line having charge storage patterns on a substrate. A peripheral line is disposed on one side of the word line group so that the edge word line is between the peripheral word line and the middle word lines. The peripheral line includes an insulating layer and a gate electrode. Charge storage patterns of the middle and edge word lines are separated from each other, and a charge storage pattern of the edge word line extends on one side to be connected to the insulating layer of the peripheral line. Methods of forming nonvolatile memory devices are also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.