Structure and method for screening SRAMS
US8064279B2 · kind B2 · utility
4Cited by
3References
20Claims
0Family size
Assignee
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Key dates
| Filing date | Jul 14, 2009 |
| Grant date | Nov 22, 2011 |
| Priority date | — |
| Expiry date | Aug 3, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/1202
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit containing an SRAM that provides a switch to decouple the SRAM wordline voltage from the SRAM array voltage during screening and that also provides different wordline and array voltages during a portion of the SRAM bit screening test. A method for screening SRAM bits in an SRAM array in which the wordline voltage is different than the array voltage during a portion of the screening test.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.