Methods and apparatuses for circuit simulation
US8065129B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 19, 2004 |
| Grant date | Nov 22, 2011 |
| Priority date | — |
| Expiry date | Feb 11, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/367
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and apparatuses for transient simulation of circuits. One embodiment of the present invention eliminates the inductive branch current variables in terms of node voltage variables to generate a linear equation system with a sparse, symmetric and positive definite matrix, which can be solved efficiently using a pre-conditioned conjugate gradient method. The known vector of the linear equation system includes the contribution from the known inductive branch currents at a previous time instance. In one embodiment of the present invention, a node on a branch to a known voltage, such as ground, and on two resistive branches are identified and eliminated to form the linear equation system with a reduced dimension. In one embodiment of the present invention, multiple time step sizes are selectively used to balance the accuracy in transient simulation and efficiency.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.