System and method for error correction in cache units
US8065555B2 · kind B2 · utility
10Cited by
7References
28Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 28, 2006 |
| Grant date | Nov 22, 2011 |
| Priority date | — |
| Expiry date | Aug 18, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1064
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and a processor may include storing a first set of data in a data array in a cache unit substantially concurrently to reading a second set of data from the data array, and using the second set of data to generate error correction data corresponding to the first set of data. A method or processor may include reading an entry from a cache in a processor and executing two or more error detection mechanisms on the entry substantially concurrently.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.