Method and apparatus for tracking, reporting and correcting single-bit memory errors
US8065573B2 · kind B2 · utility
14Cited by
15References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 19, 2008 |
| Grant date | Nov 22, 2011 |
| Priority date | — |
| Expiry date | Jun 30, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/09
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Various embodiments include an apparatus comprising a memory device including a plurality of addressable memory locations, and a memory manager coupled to the memory device, the memory manager including a scheduling unit and a histogram data structure including a plurality of counters, the scheduling unit operable to detect a single-bit error in data read from the memory device, and to increment a value in a particular one of the plurality of counters, the particular one of the plurality of counters corresponding to the particular bit in the accessed data which incurred the single-bit error in the read data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.