Patent · US Active

Systems and methods for reduced test case generation

US8065640B1 · kind B1 · utility

9Cited by

7References

21Claims

0Family size

Assignee

Cadence Design Systems, Inc. · US

Inventors

Sascha Richter · Munich, DE
Denis Baylor · Cupertino, US

Key dates

Filing date	May 30, 2007
Grant date	Nov 22, 2011
Priority date	—
Expiry date	Apr 23, 2030

Classification

Technology area (CPC G)Physics
CPC primaryG06F30/327
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

In one embodiment of the invention, a method is disclosed including executing one or more commands of a work script to perform work on a portion of a netlist of an integrated circuit design; receiving an indication of a program fault in a first integrated circuit (IC) design program performing work on the portion of the netlist in response to the one or more commands of the work script; and generating a debug work script associated with the work script in response to the program fault, the debug work script including an identification of the portion of the netlist of the integrated circuit design upon which work was being performed during the program fault.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.