Isolation verification for implementing modular redundancy within programmable integrated circuits
US8065642B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 18, 2008 |
| Grant date | Nov 22, 2011 |
| Priority date | — |
| Expiry date | Apr 20, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/398
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer-implemented method of verifying isolation of a plurality of instances of a redundant module of a circuit design that is implemented within a single, programmable integrated circuit can include counting component failures needed to establish a connection between at least two different ones of the plurality of instances of the redundant module. The method can include determining whether each instance of the redundant module is isolated from each other instance of the redundant module according to the counting of component failures, and outputting an indication whether each of the plurality of instances of the redundant module is isolated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.