Reducing susceptibility of circuit designs to single event upsets
US8065644B1 · kind B1 · utility
11Cited by
2References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 14, 2008 |
| Grant date | Nov 22, 2011 |
| Priority date | — |
| Expiry date | Jun 12, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4125
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer-implemented method of reducing susceptibility of a circuit design to single event upsets can include determining a susceptibility level of the circuit design to single event upsets, comparing the susceptibility level with a target susceptibility, and selectively applying a mitigation technique to at least one of a plurality of regions of the circuit design when the susceptibility level of the circuit design exceeds the target susceptibility. The circuit design including the mitigated region can be output.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.