Techniques for use with automated circuit design and simulations
US8065650B2 · kind B2 · utility
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14References
20Claims
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Key dates
| Filing date | Jul 25, 2008 |
| Grant date | Nov 22, 2011 |
| Priority date | — |
| Expiry date | Apr 29, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus having two or more parallel carry chain structures, each of the carry chain structures comprising a series of logical structures, where at least one of the logical structures within each of the carry chain structures has an associated input node, output node and carry node. The input node corresponds to a function input term, the output node corresponds to an output term of the function and the carry node corresponds to a carry value to a following logical structure in the series of logical structures.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.