Asymmetric segmented channel transistors

US8067287B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventor

• Peter Baumgartner · Munich, DE

Key dates

• Filing date: Feb 25, 2008
• Grant date: Nov 29, 2011
• Expiry date: May 1, 2030

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/60

Abstract

Structures, layouts and methods of forming integrated circuits are described. In various embodiments, the current invention includes an asymmetric segmented transistor. The asymmetric segmented transistor includes a source region and a drain region disposed within an active region, a floating source/drain region disposed within the active region, a first channel region disposed in the active region between the source region and the floating source/drain region, the first channel having a first length and a first width. A second channel region is disposed in the active region between the drain region and the floating source/drain region, the second channel having a second length and a second width. A first gate dielectric overlies the first channel region and a second gate dielectric overlies the second channel region. A gate line overlies the first gate dielectric and the second gate dielectric.