Techniques for placement of active and passive devices within a chip
US8067816B2 · kind B2 · utility
6Cited by
1References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 3, 2009 |
| Grant date | Nov 29, 2011 |
| Priority date | — |
| Expiry date | Jul 3, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor die includes a semiconductive substrate layer with first and second sides, a metal layer adjacent the second side of the semiconductive substrate layer, one or more active devices in an active layer on the first side of the semiconductive substrate layer; and a passive device in the metal layer in electrical communication with the active layer. The passive device can electrically couple to the active layer with through silicon vias (TSVs).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.