Method of fabricating efuse, resistor and transistor
US8071437B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 19, 2009 |
| Grant date | Dec 6, 2011 |
| Priority date | — |
| Expiry date | Jun 10, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/811
Abstract
A method of fabricating an efuse, a resistor and a transistor includes the following steps: A substrate is provided. Then, a gate, a resistor and an efuse are formed on the substrate, wherein the gate, the resistor and the efuse together include a first dielectric layer, a polysilicon layer and a hard mask. Later, a source/drain doping region is formed in the substrate besides the gate. After that, the hard mask in the resistor and the efuse is removed. Subsequently, a salicide process is performed to form a silicide layer on the source/drain doping region, the resistor, and the efuse. Then, a planarized second dielectric layer is formed on the substrate and the polysilicon in the gate is exposed. Later, the polysilicon in the gate is removed to form a recess. Finally a metal layer is formed to fill up the recess.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.