Low loss substrate for integrated passive devices

US8071461B2 · kind B2 · utility

Assignee

• Freeescale Semiconductor, Inc. · US

Inventors

• Xiaowei Ren · Phoenix, US
• Wayne R. Burger · Phoenix, US
• Colin Kerr · Dartmouth, CA
• Mark Arwyn Bennett · Leatherhead, GB

Key dates

• Filing date: Dec 4, 2008
• Grant date: Dec 6, 2011
• Expiry date: Jan 31, 2030

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D89/10
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Electronic elements (44, 44′, 44″) having an active device region (46) and integrated passive device (IPD) region (60) on a common substrate (45) preferably include a composite dielectric region (62, 62′, 62″) in the IPD region underlying the IPD (35) to reduce electromagnetic (E-M) (33) coupling to the substrate (45). Mechanical stress created by plain dielectric regions (36′) and its deleterious affect on performance, manufacturing yield and occupied area may be avoided by providing electrically isolated inclusions (65, 65′, 65″) in the composite dielectric region (62, 62′, 62″) of a material having a thermal expansion coefficient (TEC) less than that of the dielectric material (78, 78′, 78″) in the composite dielectric region (62, 62′, 62″). For silicon substrates (45), non-single crystal silicon is suitable for the inclusions (65, 65′, 65″) and silicon oxide for the dielectric material (78, 78′, 78″). The inclusions (65, 65′, 65″) preferably have a blade-like shape separated by and enclosed within the dielectric material (78, 78′, 78″).