Patent · US Active

Method of semiconductor manufacturing for small features

US8071485B2 · kind B2 · utility

16Cited by
1References
19Claims
0Family size

Assignee

Inventors

Key dates

Filing dateJun 29, 2009
Grant dateDec 6, 2011
Priority date—
Expiry dateJan 20, 2030

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH01L21/0337
  • WIPO fieldSemiconductors
  • WIPO sectorElectrical engineering

Abstract

Small feature patterning is accomplished using a multilayer hard mask (HM). Embodiments include sequentially forming a first HM layer and a multilayer HM layer over a substrate, the multilayer HM layer comprising sublayers, etching the multilayer HM layer to form a first opening having an upper first opening with sides converging to a lower second opening and a second opening with substantially parallel sides and an opening substantially corresponding to the lower second opening of the first opening, etching through the second opening to form a corresponding opening in the first HM layer, and etching the substrate through the corresponding opening in the first HM layer.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.