Programmable logic device architecture with the ability to combine adjacent logic elements for the purpose of performing high order logic functions
US8072238B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 16, 2010 |
| Grant date | Dec 6, 2011 |
| Priority date | — |
| Expiry date | Sep 16, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17728
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A high efficiency PLD architecture having logic elements that can be selectively combined to perform higher order logic functions than can be performed alone by a single logic element. The programmable logic device includes a logic block having a first logic element. The first logic element includes a first pair of sub-function generators and is capable of implementing logic functions of a first order. The logic block also includes a second logic element having a second pair of sub-function generators. A programmable sharing circuitry is also included in the logic block. The programmable sharing circuitry selectively couples the first pair of sub-function generators and the second pair of sub-function generators so that the first logic element is capable of performing logic functions of either (i) the first order, or (ii) a second order. The second order is higher than the first order.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.