Method and apparatus for testing a full system integrated circuit design by statistical fault injection using hardware-based simulation

US8073668B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Jeffrey William Kellington · Pflugerville, US
• Prabhakar Kudva · New York, US
• Naoko Pia Sanda · Chappaqua, US
• John A. Schumann · Austin, US

Key dates

• Filing date: Jan 30, 2008
• Grant date: Dec 6, 2011
• Expiry date: May 25, 2030

Classification

• Technology area (CPC G): Physics
• CPC primary: G01R31/31816
• WIPO field: Measurement
• WIPO sector: Instruments

Abstract

A test system tests a full system integrated circuit (IC) model that includes a device under test (DUT) IC model and a support IC model. A test manager information handling system (IHS) maps the full system IC model on a hardware accelerator simulator via an interface bus. The hardware accelerator simulator thus emulates the full system IC model. Of all possible fault injection points in the model, the test manager IHS selects a subset of those injection points for fault injection via a statistical sampling method in one embodiment. In response to commands from the test manager IHS, the simulator serially injects faults into the selected fault injection points. The test manager IHS stores results for respective fault injections at the selected injection points. If a machine checkstop or silent data corruption error occurs as a result of an injected fault, the DUT IC model may return to a stored checkpoint and resume operation from the stored checkpoint. The result information is useful in determining a soft error rate (SER) for the DUT IC.