Protecting data on integrated circuit
US8074132B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 28, 2008 |
| Grant date | Dec 6, 2011 |
| Priority date | — |
| Expiry date | Dec 21, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31719
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Various example embodiments are disclosed. According to one example embodiment, an integrated circuit may include a mode block, a plurality of data blocks, and a reset node. The mode block may be configured to output a test mode signal, a scan mode signal, and a trigger signal based on a received data input. The plurality of data blocks may each include registers configured to store data, each of the plurality of data blocks being configured to write over at least some of the data stored in their respective registers in response to receiving a write-over instruction. The reset node may be configured to reset the registers based on receiving either a first reset input or a second reset input. The integrated circuit may be configured to enter a test mode, enter a scan mode, and exit the test mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.