Method for forming transistor with high breakdown voltage using pitch multiplication technique

US8076208B2 · kind B2 · utility

Assignee

• Micron Technology, Inc. · US

Inventor

• Mike Smith · Cambridge, US

Key dates

• Filing date: Jul 3, 2008
• Grant date: Dec 13, 2011
• Expiry date: Jul 8, 2029

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D62/151

Abstract

Transistors are formed using pitch multiplication. Each transistor includes a source region and a drain region connected by strips of active area material separated by shallow trench isolaton structures. The shallow trench isolaton structures are formed by dielectric material filling trenches that are formed by pitch multiplication. During pitch multiplication, rows of spaced-apart mandrels are formed and spacer material is blanket deposited over the mandrels. The spacer material is etched to define spacers on sidewalls of the mandrels and the mandrels are subsequently removed, thereby leaving free-standing spacers. The spacers constitute a mask, through which an underlying substrate is etched to form the trenches and strips of active area material. The trenches are filled to form the shallow trench isolaton structures. The substrate is doped to form source, drain and channel regions and a gate is formed over the channel region. In some embodiments, the shallow trench isolaton structures and the strips of material facilitate the formation of transistors having a high breakdown voltage.