Structure for inhibiting back end of line damage from dicing and chip packaging interaction failures
US8076756B2 · kind B2 · utility
19Cited by
12References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 19, 2011 |
| Grant date | Dec 13, 2011 |
| Priority date | — |
| Expiry date | Feb 19, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/18301
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor product comprises a semiconductor substrate having a top surface and a bottom surface including a semiconductor chip. The semiconductor substrate has a top surface and a perimeter. A barrier is formed in the chip within the perimeter. An Ultra Deep Isolation Trench (UDIT) is cut in the top surface of the chip extending down therein between the perimeter and the barrier. A ILD structure with low-k pSICOH dielectric and hard mask layers is formed over the substrate prior to forming the barrier and the UDIT. The ILD structure interconnection structures can be recessed down to the substrate aside from the UDIT.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.