IC interconnect
US8076768B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 3, 2010 |
| Grant date | Dec 13, 2011 |
| Priority date | — |
| Expiry date | Nov 3, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A multi-tiered IC device contains a first die including a substrate with a first and second set of vias. The first set of vias extends from one side of the substrate, and the second set of vias extend from an opposite side of the substrate. Both sets of vias are coupled together. The first set of vias are physically smaller than the second set of vias. A second die having a set of interconnects is stacked relative to the first die in which the interconnects couple to the first set of vias.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.