Bart Swinnen
11Patents
5h-index
14Co-inventors
59Inventor score
Filing activity: Dec 9, 2003 → Aug 18, 2014
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US7566634B2 | Method for chip singulation | Electricity | 46 | Active |
| US7042552B1 | Alignment strategy optimization method | Physics | 15 | Expired |
| US7939926B2 | Via first plus via last technique for IC interconnects | Electricity | 14 | Active |
| US7795113B2 | Method for bonding a die or substrate to a carrier | Emerging Cross-Sectional Technologies | 7 | Active |
| US9646930B2 | Semiconductor device having through-substrate vias | Electricity | 6 | Active |
| US7565219B2 | Lithographic apparatus, method of determining a model parameter, device manufacturing method, and device manufactured thereby | Physics | 5 | Active |
| US7985620B2 | Method of fabricating via first plus via last IC interconnect | Electricity | 5 | Active |
| US7558643B2 | Lithographic apparatus, method of determining a model parameter, device manufacturing method, and device manufactured thereby | Physics | 2 | Active |
| US8809188B2 | Method for fabricating through substrate vias | Electricity | 2 | Active |
| US10332850B2 | Method for producing contact areas on a semiconductor substrate | Electricity | 1 | Active |
| US8076768B2 | IC interconnect | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.