Low leakage data retention flip flop
US8076965B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 10, 2008 |
| Grant date | Dec 13, 2011 |
| Priority date | — |
| Expiry date | Apr 10, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/012
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A disclosed embodiment is a low leakage data retention flip flop comprising a master circuit for retaining data during sleep mode, wherein the master circuit is configured to receive a reduced supply voltage during the sleep mode. The flip flop includes a slave circuit having low threshold voltage transistors, where the slave circuit is turned off during the sleep mode. In various embodiments, the master circuit might utilize high threshold voltage, standard threshold voltage, or low threshold voltage transistors. Similarly, the slave circuit might utilize high threshold voltage, standard threshold voltage, or low threshold voltage transistors. To begin the sleep mode, the master circuit receives a reduced supply voltage and the slave circuit is coupled to ground and is thus turned off. During the sleep mode, the slave circuit experiences virtually no leakage current, and the master circuit experiences a reduced leakage current.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.