Distributed VDC for SRAM memory
US8077517B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 18, 2008 |
| Grant date | Dec 13, 2011 |
| Priority date | — |
| Expiry date | May 20, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C5/147
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit structure includes a memory. The memory includes a first memory macro and a second memory macro identical to the first memory macro. A first power block is connected to the first memory macro and is configured to provide a regulated voltage to the first memory macro. The first power block has a first input and a first output. A second power block substantially identical to the first power block is connected to the second memory macro and is configured to provide the regulated voltage to the second memory macro. The second power block has a second input and a second output. The first input and the second input are interconnected. The first output and the second output are interconnected.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.