Structure for implementing speculative clock gating of digital logic circuits
US8078999B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 30, 2008 |
| Grant date | Dec 13, 2011 |
| Priority date | — |
| Expiry date | Mar 7, 2030 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A design structure embodied in a non-transitory machine readable medium used in a design process includes an apparatus for implementing speculative clock gating of digital logic circuits, including operation valid logic configured to generate, in a first pipeline stage n, a valid control signal input to a first register in a second pipeline stage n+1, the valid control signal indicative of when an operation is qualified to be performed by the second pipeline stage n+1; and speculative valid logic configured to generate, in the first pipeline stage, a speculative valid control signal used to gate a clock signal to a plurality of additional registers in the second pipeline stage, wherein the speculative valid control signal is generated using only a subset of a total number of control inputs used in generating the valid control signal, and wherein the clock signal is sent directly to the first register. The design structure includes a netlist describing the apparatus for implementing speculative clock gating of digital logic circuits included in a multiple stage pipeline design.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.