Method and apparatus for evaluating paths in an integrated circuit design
US8079002B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 24, 2008 |
| Grant date | Dec 13, 2011 |
| Priority date | — |
| Expiry date | Nov 4, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/39
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An embodiment of the invention involves: providing a database that includes layout information representing a layout within an integrated circuit of an electrical circuit; identifying from the information in the database each conductive path of a selected type in the electrical circuit; extracting layout information from the database for each conductive path of the selected type; and calculating an electrical parameter for each conductive path of the selected type, as a function of the layout information obtained for that conductive path during the extracting. In addition, in a different configuration of the embodiment, a report can be generated containing information based on the electrical parameter calculated during the calculating for at least one of the conductive paths of the selected type.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.