Efficient exhaustive path-based static timing analysis using a fast estimation technique
US8079004B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 30, 2009 |
| Grant date | Dec 13, 2011 |
| Priority date | — |
| Expiry date | Mar 10, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
One embodiment of the present invention provides a system that performs an efficient path-based static timing analysis (STA) in a circuit design. During operation, the system identifies a set of paths within the circuit design, wherein each path includes one or more segments. For a path in the set of paths, the system determines if at least one segment in the path is shared with a different path which was previously computed by performing a path-based STA, wherein the at least one segment in the different path is associated with previously computed path-based timing information. If so, the system then performs an estimation of a path-based delay for the path based at least on the path-based timing information associated with the shared segment in the different path. Otherwise, the system computes a path-based delay for the path by performing a path-based STA on the path.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.