Method for mitigating imprint in a ferroelectric memory
US8081500B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 31, 2009 |
| Grant date | Dec 20, 2011 |
| Priority date | — |
| Expiry date | Aug 28, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/005
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An array of ferroelectric memory cells that allows imprint mitigation includes ferroelectric memory cells respectively coupled to word lines, plate lines, and bit lines; a word line driver for driving the word lines; a plate line driver for driving the plate lines; a bit line driver for driving the bit lines; and an isolation device driver for driving isolation devices coupled between the bit lines and a plurality of bit lines. The method for mitigating imprint includes coupling the bit lines to a respective plurality of sense amplifiers, turning on a word line and pulsing a plate line associated with a row of ferroelectric memory cells, disconnecting the bit lines from the respective sense amplifiers, driving the plate line low and the bit lines high, driving the plate line high and the bit lines low, driving the plate line low and floating the bit lines, driving the bit lines with the sense amplifier, and turning off the word line and precharging the bit lines. The method can be performed after each memory access, or can be performed whenever convenient with a counter and a rejuvenate command.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.