Multi-level nonvolatile memory device using variable resistive element
US8081501B2 · kind B2 · utility
17Cited by
3References
17Claims
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Key dates
| Filing date | Mar 5, 2009 |
| Grant date | Dec 20, 2011 |
| Priority date | — |
| Expiry date | Dec 11, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/72
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multi-level nonvolatile memory device using variable resistive element with improved reliability of read operations is provided. A multi-level nonvolatile memory device comprises a multi-level memory which includes a resistance element, wherein the resistance level of the resistance element is variable depending on data stored in the multi-level memory cell, and a read circuit which provides the multi level memory cell with a read bias and performs a sensing operation in response to the read bias, wherein the read bias has at least two levels during a read cycle.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.