Memory elements with body bias control

US8081502B1 · kind B1 · utility

Assignee

• Altera Corporation · US

Inventors

• Irfan Rahim · Milpitas, US
• Jun Liu · 红钢城街道, CN
• Andy L. Lee · San Jose, US
• William Bradley Vest · San Jose, US
• Lu Zhou · Santa Clara, US
• Qi Xiang · San Jose, US
• Yanzhong Yu · Santa Clara, US
• Jeffrey Tung · Milpitas, US
• Albert Ratnakumar · San Jose, US

Key dates

• Filing date: Dec 29, 2008
• Grant date: Dec 20, 2011
• Expiry date: Jun 2, 2029

Classification

• Technology area (CPC G): Physics
• CPC primary: G11C11/412
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

An integrated circuit with memory elements is provided. The memory elements may have memory element transistors with body terminals. Body bias control circuitry may supply body bias voltages that strengthen or weaken memory element transistors to improve read and write margins. The body bias control circuitry may dynamically control body bias voltages so that time-varying body bias voltages are supplied to memory element transistors. Address transistors and latch transistors in the memory elements may be selectively strengthened and weakened. Process variations may be compensated by weakening fast transistors and strengthening slow transistors with body bias adjustments.