Two bits per cell non-volatile memory architecture
US8081521B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 13, 2009 |
| Grant date | Dec 20, 2011 |
| Priority date | — |
| Expiry date | Jul 6, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0441
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory circuit for holding a single binary value. A first bit cell holds one of a logical high value and a logical low value, and a second bit cell also holds one of a logical high value and a logical low value. Circuitry is provided for placing a logical high value in the first bit cell when the binary value in the memory circuit is to be a logical high value, and circuitry is provided for placing a logical high value in the second bit cell when the binary value in the memory circuit is to be a logical low value. In this manner, a logical high value exists within the memory circuit, whether the single binary value within the memory circuit is a logical high value or a logical low value. The difference between the two values of the binary value is which of the two bit cells holds the logical high value. Thus, this memory circuit can be sensed without the use of a sense amplifier.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.