Method and apparatus for thermal modeling and analysis of semiconductor chip designs
US8082137B2 · kind B2 · utility
6Cited by
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27Claims
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Key dates
| Filing date | Jun 11, 2008 |
| Grant date | Dec 20, 2011 |
| Priority date | — |
| Expiry date | Aug 20, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for modeling and thermal analysis of semiconductor chip designs is provided. One embodiment of a novel method for performing thermal testing of a semiconductor chip design includes calculating full-chip temperatures over the semiconductor chip design (e.g., to identify steep thermal gradients) and modeling the full-chip temperatures in accordance with a geometric multi-grid technique. The geometric multi-grid technique is tailored to determine temperatures within the semiconductor chip design based at least in part on the physical attributes or geometry of the design.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.