Automated bottom-up and top-down partitioned design synthesis
US8082138B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 13, 2003 |
| Grant date | Dec 20, 2011 |
| Priority date | — |
| Expiry date | Dec 5, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An embodiment of the present invention includes a partitioner, a synthesizer, and an optimizer. The partitioner partitions a design into a hierarchy of partitions having a top-level partition and lower partitions. The lower partitions include a bottom-level partition. The top-level partition has top-level constraints. The synthesizer synthesizes the lower partitions hierarchically from the bottom-level partition to create lower partition netlists based on the top-level constraints. The optimizer optimizes a top-level netlist corresponding to the top-level partition from the lower partition netlists to satisfy the top-level constraints.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.