Matched multiplier circuit having reduced phase shift for use in MEMS sensing applications
US8082789B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 2, 2008 |
| Grant date | Dec 27, 2011 |
| Priority date | — |
| Expiry date | Oct 25, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01P15/13
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Apparatus and methods are provided for multiplier circuits having reduced phase shift. A multiplier circuit comprises an input node for an input signal and an output node for an output signal. A first multiplier is coupled to the input node and has a first multiplier output, wherein the first multiplier multiplies the input signal by a first signal to produce a second signal at the first multiplier output. A second multiplier is coupled to the output node and is matched to the first multiplier. The second multiplier multiplies the output signal by a third signal to produce a fourth signal at a second multiplier output. An amplifier is coupled to the first multiplier output and the second multiplier output and produces the output signal at an amplifier output coupled to the output node based upon the second signal and the fourth signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.