Method for forming a bipolar junction transistor and a metal oxide semiconductor field effect transistor

US8084313B2 · kind B2 · utility

Assignee

• Agere Systems Inc. · US

Inventors

• Arun K. Nanda · Sammamish, US
• Venkat Raghavan · Fryeburg, US
• Nace Rossi · Singapore, SG

Key dates

• Filing date: Jul 8, 2010
• Grant date: Dec 27, 2011
• Expiry date: Jul 8, 2030

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/401

Abstract

A method for forming BiCMOS integrated circuits and structures formed according to the method. After forming doped wells and gate stacks for the CMOS devices and collector and base regions for the bipolar junction transistor, an emitter layer is formed within an emitter window. A dielectric material layer is formed over the emitter layer and remains in place during etching of the emitter layer and removal of the etch mask. The dielectric material layer further remains in place during source/drain implant doping and activation of the implanted source/drain dopants. The dielectric material layer functions as a thermal barrier, to limit out-diffusion of the emitter dopants during the activation step.