DRAM cell with enhanced capacitor area and the method of manufacturing the same

US8084321B2 · kind B2 · utility

Assignee

• TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD. · TW

Inventor

• Jai-Hoon Sim · Seongnam-si, KR

Key dates

• Filing date: Jun 2, 2011
• Grant date: Dec 27, 2011
• Expiry date: Jun 2, 2031

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D1/714

Abstract

A dynamic random access memory (DRAM) cell and the method of manufacturing the same are provided. The DRAM cell includes a cell transistor and a cell capacitor. The cell capacitor includes a first, second and third dielectric layer, and a first, second and third capacitor electrode. The first dielectric layer is located on a first capacitor electrode. The second capacitor electrode is located on top of the first dielectric layer. The second dielectric layer is located on the second capacitor electrode. The third capacitor electrode is located on the second dielectric layer and is electrically connected with the drain. The third dielectric layer is located between the third capacitor electrode and the gate for isolating the gate from the third capacitor electrode.