Nonvolatile semiconductor memory device
US8084830B2 · kind B2 · utility
67Cited by
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15Claims
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Key dates
| Filing date | Sep 9, 2009 |
| Grant date | Dec 27, 2011 |
| Priority date | — |
| Expiry date | Feb 27, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B63/80
Abstract
The memory cell is located at respective intersections between the first wirings and the second wirings. Each of the memory cells has a rectifier element and a variable resistance element connected in series. The rectifier element includes a p type first semiconductor region, and a n type second semiconductor region. The first semiconductor region is formed of, at least in part, silicon-germanium mixture (Si1-xGex (0<x<=1)). The second semiconductor region is formed of silicon (Si).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.