Wear level estimation in analog memory cells
US8085586B2 · kind B2 · utility
29Cited by
247References
18Claims
0Family size
Assignee
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Key dates
| Filing date | Dec 25, 2008 |
| Grant date | Dec 27, 2011 |
| Priority date | — |
| Expiry date | Aug 19, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3495
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for operating a memory includes applying at least one pulse to a group of analog memory cells, so as to cause the memory cells in the group to assume respective storage values. After applying the pulse, the respective storage values are read from the memory cells in the group. One or more statistical properties of the read storage values are computed. A wear level of the group of the memory cells is estimated responsively to the statistical properties.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.