Charge-trap flash memory device with reduced erasure stress and related programming and erasing methods thereof
US8085592B2 · kind B2 · utility
6Cited by
3References
5Claims
0Family size
Assignee
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Key dates
| Filing date | Jan 20, 2009 |
| Grant date | Dec 27, 2011 |
| Priority date | — |
| Expiry date | Dec 7, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Operation methods of charge-trap flash memory devices having an unused memory cell for data storage and a normal memory cell used for data storage are discussed. The operation method may include selecting the unused memory cell, and programming the unused memory cell to have a predetermined threshold voltage. The charge-trap flash memory device may thus be provided with improved reliability by interrupting erasure stress to unused memory cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.