Page buffer circuit, nonvolatile memory device including the page buffer circuit, and method of operating the nonvolatile memory device
US8085602B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 21, 2011 |
| Grant date | Dec 27, 2011 |
| Priority date | — |
| Expiry date | Jan 21, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0483
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A page buffer circuit comprises a bit line selection unit, a latch unit, and a bit line control unit. The bit line selection unit is configured to select a bit line coupled to memory cells. The latch unit comprises a plurality of latch circuits. The plurality of latch circuits is coupled to a sense node and configured to latch data to be programmed into the memory cells or store data from the memory cells. The bit line control unit is coupled to the sense node and configured to temporarily charge a voltage of the selected bit line in response to charge and transfer control signals or transfer the charged voltage to the selected bit line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.