Loading data to vector renamed register from across multiple cache lines
US8086801B2 · kind B2 · utility
3Cited by
11References
20Claims
0Family size
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Key dates
| Filing date | Apr 8, 2009 |
| Grant date | Dec 27, 2011 |
| Priority date | — |
| Expiry date | Jun 23, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0886
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A load instruction that accesses data cache may be off natural alignment, which causes a cache line crossing to complete the access. The illustrative embodiments provide a mechanism for loading data across multiple cache lines without the need for an accumulation register or collection point for partial data access from a first cache line while waiting for a second cache line to be accessed. Because the accesses to separate cache lines are concatenated within the vector rename register without the need for an accumulator, an off-alignment load instruction is completely pipeline-able and flushable with no cleanup consequences.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.