Power aware asynchronous circuits
US8086975B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Apr 10, 2009 |
| Grant date | Dec 27, 2011 |
| Priority date | — |
| Expiry date | Apr 1, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/35
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques are described for converting netlists for synchronous circuits such as combinational modules, flip flops (or latches), and clock gating modules, to netlist of asynchronous modules. Processes including algorithms are described that bundle multiple modules in an enable domain, so that they are activated only if the incoming enable token to the enable domain has the UPDATE value. The modules can be clustered inside an enable domain, so that each cluster has a separate controller. The objective function of bundling and clustering can minimize power consumption with respect to a given cycle time. Exemplary embodiments can include a gated multilevel domino template.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.