Methods and systems for reducing clock skew in a gated clock tree
US8086982B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 4, 2009 |
| Grant date | Dec 27, 2011 |
| Priority date | — |
| Expiry date | Apr 20, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2117/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods for synthesizing a gated clock tree with reduced clock skew are provided. A gated clock tree circuit with reduced clock skew may include a clock source and edge-triggered state elements. A gated clock tree disposed between the clock source and state elements may include a level in which each logic gate has a common logic type. Logic gates in the gated clock tree may also be configured as logic-gate buffers. The logic gates may also be configured as NAND-gated equivalents. The clock signal distributed through the gated clock tree may drive both positive-edge-triggered and negative-edge-triggered state elements.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.