Bumping free flip chip process
US8088647B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 20, 2010 |
| Grant date | Jan 3, 2012 |
| Priority date | — |
| Expiry date | Jul 21, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/14
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods, systems, and apparatuses for an integrated circuit package assembly process are provided. A wafer is received having a surface defined by a plurality of integrated circuit regions. Electrical conductors are accessible through corresponding first openings in a first passivation layer on the surface of the wafer. Solderable metal layer features are formed on the electrical conductors through the first openings. The wafer is singulated to form a plurality of flip chip dies. A plurality of package substrates is received. Each package substrate has a plurality of solder on pad (SOP) features on a respective surface. Each flip chip die is mounted to a corresponding package substrate such that each SOP feature is coupled to a corresponding solderable metal layer feature, to form a plurality of integrated circuit packages.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.