Inventor · Ladera Ranch, CA, US

Edward Law

22Patents
6h-index
25Co-inventors
65Inventor score

Filing activity: Nov 30, 2001 → Dec 2, 2019

Most-cited inventions

PatentTitleAreaCited byStatus
US7259445B2 Thermal enhanced package for block mold assembly Electricity 74 Expired
US6882042B2 Thermally and electrically enhanced ball grid array packaging Electricity 40 Expired
US8367475B2 Chip scale package assembly in reconstitution panel process format Electricity 27 Active
US8587123B2 Multi-chip and multi-substrate reconstitution based packaging Electricity 8 Active
US8686558B2 Thermally and electrically enhanced ball grid array package Electricity 7 Active
US8957694B2 Wafer level package resistance monitor scheme Electricity 7 Active
US10008439B2 Thin recon interposer package without TSV for fine input/output pitch fan-out Electricity 5 Active
US8922014B2 Wafer level semiconductor package Electricity 5 Active
US8779598B2 Method and apparatuses for integrated circuit substrate manufacture Electricity 4 Active
US7629681B2 Ball grid array package with patterned stiffener surface and method of assembling the same Electricity 4 Expired
US8169067B2 Low profile ball grid array (BGA) package with exposed die and method of making same Electricity 4 Active
US7091469B2 Packaging for optoelectronic devices Electricity 3 Expired
US9693461B2 Magnetic-core three-dimensional (3D) inductors and packaging integration Electricity 3 Active
US9564391B2 Thermal enhanced package using embedded substrate Electricity 2 Active
US8592259B2 Method of fabricating a wafer level semiconductor package having a pre-formed dielectric layer Electricity 2 Active
US10615110B2 Thin recon interposer package without TSV for fine input/output pitch fan-out Electricity 1 Active
US9390993B2 Semiconductor border protection sealant Electricity 1 Active
US8039949B2 Ball grid array package having one or more stiffeners Electricity 1 Active
US8945991B2 Fabricating a wafer level semiconductor package having a pre-formed dielectric layer Electricity 0 Active
US11049829B2 Redistribution metal and under bump metal interconnect structures and method Electricity 0 Active
US8088647B2 Bumping free flip chip process Electricity 0 Active
US10504862B2 Redistribution metal and under bump metal interconnect structures and method Electricity 0 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.