Fuse link structures using film stress for programming and methods of manufacture
US8089105B2 · kind B2 · utility
8Cited by
5References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 4, 2010 |
| Grant date | Jan 3, 2012 |
| Priority date | — |
| Expiry date | Nov 4, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a programmable fuse structure includes forming at least one shallow trench isolation (STI) in a substrate, fanning an e-fuse over the at least one STI and depositing an interlevel dielectric (ILD) layer over the e-fuse. Additionally, the method includes removing at least a portion of the at least one STI under the e-fuse to provide an air gap below a portion of the e-fuse and removing at least a portion of the ILD layer over the e-fuse to provide the air gap above the portion of the e-fuse.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.