Patent · US Active

Synchronous multi-clock protocol converter

US8089378B1 · kind B1 · utility

3Cited by

7References

17Claims

0Family size

Assignee

Marvell Israel (M.I.S.L) Ltd. · IL

Inventors

Gil Stoler · Nofit, IL
Eitan Joshua · Ramot Menashe, IL
Shaul Chapman · Netanya, IL

Key dates

Filing date	Feb 16, 2010
Grant date	Jan 3, 2012
Priority date	—
Expiry date	Feb 16, 2030

Classification

Technology area (CPC H)Electricity
CPC primaryH03M5/02
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

Some of the embodiments of the present disclosure provide a method of transferring data from a fast clock domain associated with a fast clock signal to a slow clock domain associated with a slow clock signal, the method comprising receiving first fast data from the fast clock domain during a first fast clock cycle, wherein the first fast clock cycle is a first full fast clock cycle in a first slow clock cycle; and propagating, during the first full fast clock cycle in the first slow clock cycle, the received first fast data to the slow clock domain. Other embodiments are also described and claimed.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.