Tiled prefetched and cached depth buffer

US8089486B2 · kind B2 · utility

Assignee

• QUALCOMM Incorporated · US

Inventors

• Michael H. Anderson · Conway, US
• Dan Chuang · San Jose, US
• Geoffrey Shippee · Shields, US
• Rajat Dhawan · San Diego, US
• Chun Yu · San Diego, US

Key dates

• Filing date: Mar 21, 2005
• Grant date: Jan 3, 2012
• Expiry date: Apr 20, 2027

Classification

• Technology area (CPC G): Physics
• CPC primary: G06T15/005
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A 3D graphics pipeline includes a prefetch mechanism that feeds a cache of depth tiles. The prefetch mechanism may be predictive, using triangle geometry information from previous pipeline stages to pre-charge the cache, thereby allowing for an increase in memory bandwidth efficiency. A z-value compression technique may be optionally utilized to allow for a further reduction in power consumption and memory bandwidth.